1. Field of the Invention
The invention relates generally to non-volatile memory devices and more particularly to systems and methods for correcting an over-erase condition in a non-volatile memory cell.
2. Background of the Invention
Non-volatile memory devices, such as flash based memory devices, comprise a plurality of cells that can be electrically programmed and erased. Each cell generally represents a bit of information and cells are typically arranged into words, where each word comprises a certain number of bits. Each cell also typically comprises one or more transistors. In order to reduce the overall size of a non-volatile memory circuit, single transistor cells are often preferred. One well known type of single transistor cell used in conventional non-volatile memory devices makes use of a single transistor with a special construction known as a floating gate construction, and is referred to as a floating gate transistor.
There are three main operations performed on a flash cell, e.g., comprising a floating gate transistor. These operations are read, write, and erase. The write operation can also be referred to as a programming operation. Typically, a non-volatile memory device, e.g., a flash based memory device, is erased and then programmed with instructions or code. In operation, the code is then accessed and read by a device such as a processor. A flash cell can be read, written to, and erased by applying the appropriate voltages to the control gate, source, drain, and body, or substrate comprising, e.g., the floating gate transistor that makes up the cell.
A cell is programmed, for example, by applying a relatively high programming voltage to the control gate and a lower voltage to the drain. For example, conventional device often use a control gate voltage of 9-10 volts and a drain voltage of 5 volts during programming. The source voltage is typically maintained at ground, or 0 volts. The programming voltages are configured to create a relatively high voltage potential between the drain and source, which causes electrons to flow from source to drain through a channel in the substrate that links the two. Additionally, the relatively high voltage applied to the control gate raises the voltage potential of the floating gate, which resides below the control gate and above the channel. The floating gate is typically insulated from the substrate by a dielectric layer. Similarly, the floating gate is also insulated from the control gate by a dielectric layer. The high potential created on the floating gate attracts electrons flowing through the channel, causing them to “tunnel” through the dielectric layer separating the floating gate from the channel. This phenomenon is often referred to as hot carrier injection.
A successful programming operation results in injection of enough electrons onto the floating gate to achieve a desired threshold voltage (Vt) for the flash cell. The threshold voltage (Vt) is the voltage that must be applied to control gate to cause conduction through the channel during a read operation.
Upon removal of the programming voltages, the injected electrons are trapped on the floating gate, creating a negative voltage that must be overcome in order to effect a read. The threshold voltage (Vt) needed to overcome the negative effect of the injected electrons can for example be 4 volts; however, The threshold voltage (Vt) can vary by implantation. Moreover, as discussed below, the threshold voltage (Vt) can vary by cell due to process variations.
A cell is read by applying a read voltage to the control gate, and a lower voltage to the drain, while grounding the source. For example, a voltage of 5 volts can be applied to the control gate and a voltage of 1 volt to the drain. Current on the bit line (BL) is then sensed to determine whether the cell is programmed. If the cell is programmed and the threshold voltage (Vt) is relatively high, e.g., 4 volts, then the bit line (BL) current will be approximately 0 amps. If the cell is not programmed and the threshold voltage is relatively low, e.g., 2 volts, then the read voltage applied to the control gate will enhance the channel and the BL current will be relatively high.
A cell can be erased by applying a high voltage to the source, a lower voltage to the control gate, and allowing the drain to float. For example, a voltage of 16 volts can be applied to the source, while the control gate is grounded, or a lower voltage, such as 5 volts can be applied to the source, while a negative voltage, such as 10 volts, is applied to the control gate. This causes the electrons injected onto the floating gate to undergo a phenomenon known as Fowler-Nordheim tunneling from the floating gate, through the dielectric layer separating the floating gate from the channel, and to source. In addition, the channel is also erased by letting the drain and source float and applying an erase voltage to the control gate.
A problem with conventional non-volatile memory devices is that the manufacturing variances can cause some cells to become “over-erased” before other cells are sufficiently erased. In over-erased cells, the floating gate has a very low negative charge, or even a positive charge. An over-erased cell can act as a depletion mode transistor that cannot be turned off by normal operating voltages. Thus, an over-erased cell will have an associated leakage current that can prevent accurate reads of not just the over-erased cell, but other cells coupled with the same BL.
Conventional non-volatile memory devices implement a variety of techniques to correct over-erased cells. For example, some conventional device use a process referred to as soft-programming; however, soft-programming and other conventional solutions can be inefficient because they require extra circuitry and can significantly increase the time associated with the erase cycle. As a result, such conventional solutions may not be sufficient for certain applications that require fast erase cycles and reduced complexity.